The present invention relates generally to digital signal processing circuitry and, more particularly, to digital signal processor circuits for detecting a specific pattern or patterns including synchronization (sync) signals as contained for successive transmission in digitized 1-bit serial data read out of recording media, and for performing data demodulation with respect to digital data being transferred in succession after a sync pattern to thereby reconstruct or reproduce the original digital data.
Conventionally, digital signal processor circuits of this type include an information playback system adaptable for use in reproducing information signals pre-recorded on an optical storage medium, typically, a disk-shaped optical record carrier body known as "compact disc (CD)." One typical CD record/playback architecture has been disclosed in, for example, "CD--from Audio to PCs" by Kenji Hayashi under the supervision of Fujio Mari, Corona Publishing Co., Ltd., at pp. 13-15 and 62-63. A digital signal processor as taught thereby is designed so that for a stream of digital data bits arrayed in a time sequential manner for recording on disks, a group of data in units of "clusters" of 8 bits may be used to constitute a single frame, and wherein after completion of error correction code addition and inter-frame interleaving as well as sub-code addition, a specific modulation technique, known as the "Eight-to-Fourteen Modulation (EFM)," is employed to modulate the resulting data in units of 8-bit clusters into data with 14 bits being used as a unit to thereby add thereto a margin of 3 bits. A pattern corresponding to a synchronization signal in units of frames, each of which is made up of a plurality of data items with a cluster of 17 bits added with margin bits being as a unit; thereafter, the resultant data is recorded as one (1)-bit serial data on an associative disk in the form of recording marks called the "pits."
During reproduction of data recorded on an optical disk, a disk playback signal that is read by a pickup module from the disk is transferred via a phase locked loop (PLL) circuit as data of 1-bit serial form having a train of bits "0s" and "1s" synchronously with bit clocks. Then, serial-to-parallel conversion processing is applied to this serial data stream to thereby detect one or several sync patterns that are contained in the read data stream. The serial data stream after detection of the sync pattern(s) is converted into a 14-bit parallel data stream, which is then subject to demodulation processing thereby obtaining the demodulated, original data in units of 8-bit segments, which will be written into an associative random-access memory (RAM). Thereafter, control a read/write operation of the RAM to execute error correction through decoding of error codes and de-interleaving processing so that the original time-sequential data may be reproduced.